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 -- Copyright (C) 2005 IMEC                                                  -
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 -- File           : VideoTimingGen.vhd
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 -- Description    : VHDL entity and architecture for VideoTimingGen
 -- --------------------------------------------------------------------------
 -- Author         : Geert Vanwijnsberghe
 -- Date           : 10/2/06
 -- Version        : 1.0
 -- Change history : 
 -----------------------------------------------------------------------------
   
-- Add VHDL libraries
library ieee;
library Const_lib;
use Const_lib.constants_pack.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

ENTITY VideoTimingGen IS
  PORT(
    Clk           : in std_logic;  
    Clk_en        : in std_logic; 
    Reset_n       : in std_logic; -- synchronous active low
    Hsync         : out std_logic;
    Vsync         : out std_logic;
    Hcount        :	out std_logic_vector(10 downto 0);
    Vcount        : out std_logic_vector(10 downto 0);
    Start_video   : out std_logic;
    Video_on      : out std_logic
  );
end VideoTimingGen;

architecture behav of VideoTimingGen is
    signal internal_count_h, internal_count_v : unsigned (10 downto 0);
    signal video_on_h, video_on_v: std_logic;
    begin
        
-- add code here
-- If jou do not know how to start this job use the comments below

  --Generate Horizontal and Vertical counters
  --Sequential process
-- add code here
process (Clk)
    begin
        if (internal_count_h < H_total - 1) then
            internal_count_h <= internal_count_h + 1;
        else
            internal_count_h <= (others => '0');
            
        end if;
        
        if (internal_count_h = H_total - 1) then
            if (internal_count_v < V_total - 1) then
                internal_count_v <= internal_count_v + 1;
            else 
               internal_count_v <= (others => '0');
            end if;
        end if;
        
    end process;
    
    process (internal_count_h)
        begin
            if (internal_count_h < H_sync) then
                Hsync <= '0';
            else
                Hsync <= '1';
            end if;
        end process;
    
    process (internal_count_v)
        begin
            if (internal_count_v < V_sync) then
                Vsync <= '0';
            else
                Vsync <= '1';
            end if;
        end process;
        
    process (internal_count_h, internal_count_v)
            begin
                if ((internal_count_h >= H_sync + H_bp) and (internal_count_h < H_sync + H_bp + H_active)) then
                    video_on_h <= '1';
                else
                    video_on_h <= '0';
                end if;
                
                if ((internal_count_v >= V_sync + V_bp) and (internal_count_v < V_sync + V_bp + V_active)) then
                    video_on_v <= '1';
                else
                    video_on_v <= '0';
                end if;
            end process;
            
    process (internal_count_h, internal_count_v)
        begin
            if ((internal_count_h = H_sync + H_bp) and (internal_count_v = V_sync + V_bp)) then
                Start_video <= '1';
            else
                Start_video <= '0';
                
        end if;
    end process;
    
    Video_on <= video_on_h and video_on_v;
    
    Hcount <= std_logic_vector(internal_count_h);
    Vcount <= std_logic_vector(internal_count_v);
    
end behav;